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 STL70N4LLF5
N-channel 40 V, 0.0055 , 18 A, PowerFLATTM (6x5) STripFETTM V Power MOSFET
Preliminary Data
Features
Type STL70N4LLF5 VDSS 40 V RDS(on) max 0.0065 ID 18 A (1)
1. The value is rated according Rthj-pcb
RDS(on) * Qg industry benchmark Extremely low on-resistance RDS(on) High avalanche ruggedness Low gate drive power losses
PowerFLATTM ( 6x5 )
Application
Switching applications Figure 1. Internal schematic diagram
Description
This product utilizes the 5th generation of design rules of ST's proprietary STripFETTM technology. The lowest available RDS(on)*Qg, in this chip scale package, makes this device suitable for the most demanding DC-DC converter applications, where high power density is to be achieved.
Table 1.
Device summary
Marking 70N4LLF5 Package PowerFLATTM (6x5) Packaging Tape and reel
Order code STL70N4LLF5
December 2008
Rev 1
1/10
www.st.com 10
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Contents
STL70N4LLF5
Contents
1 2 3 4 5 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Test circuits .............................................. 6
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
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STL70N4LLF5
Electrical ratings
1
Electrical ratings
Table 2.
Symbol VDS VGS ID(1) ID (1) ID(2) ID
(3) (3)
Absolute maximum ratings
Parameter Drain-source voltage (VGS = 0) Gate-source voltage Drain current (continuous) at TC = 25 C Drain current (continuous) at TC = 100 C Drain current (continuous) at TC = 25 C Drain current (continuous) at TC=100 C Drain current (pulsed) Total dissipation at TC = 25 C Total dissipation at TC = 25 C Derating factor Value 40 22 70 44 18 11.5 72 60 4 0.03 -55 to 150 Unit V V A A A A A W W W/C C
IDM
PTOT (1) PTOT
(2)
TJ Tstg
Operating junction temperature Storage temperature
1. The value is rated according Rthj-c 2. The value is rated according Rthj-pcb 3. Pulse width limited by safe operating area
Table 3.
Symbol Rthj-case Rthj-pcb
(1)
Thermal resistance
Parameter Thermal resistance junction-case (drain) (steady state) Thermal resistance junction-ambient Value 2.08 31.3 Unit C/W C/W
1. When mounted on FR-4 board of 1inch, 2oz Cu, t < 10 sec
Table 4.
Symbol IAV EAS
Avalanche data
Parameter Not-repetitive avalanche current, (pulse width limited by Tj Max) Single pulse avalanche energy (starting TJ = 25 C, ID = IAV , VDD = 24 V) Value TBD TBD Unit A mJ
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Electrical characteristics
STL70N4LLF5
2
Electrical characteristics
(TCASE = 25 C unless otherwise specified) Table 5.
Symbol V(BR)DSS IDSS IGSS VGS(th) RDS(on)
On/off states
Parameter Drain-source breakdown voltage Zero gate voltage drain current (VGS = 0) Gate body leakage current (VDS = 0) Gate threshold voltage Static drain-source on resistance Test conditions ID = 250 A, VGS= 0 VDS = Max rating, VDS = Max rating @125 C VGS = 22 V VDS= VGS, ID = 250 A VGS= 10 V, ID= 9 A VGS= 4.5 V, ID= 9 A 1 0.0055 TBD 0.0065 0.009 Min. 40 1 10
100
Typ.
Max.
Unit V A A nA V
Table 6.
Symbol Ciss Coss Crss Qg Qgs Qgd RG
Dynamic
Parameter Input capacitance Output capacitance Reverse transfer capacitance Total gate charge Gate-source charge Gate-drain charge Test conditions VDS = 25 V, f=1 MHz, VGS=0 VDD=15 V, ID = 18 A VGS = 4.5 V (see Figure 3) f=1 MHz Gate DC Bias = 0 Test signal level = 20 mV open drain Min. Typ. 1800 270 40 13 TBD TBD Max. Unit pF pF pF nC nC nC
Gate input resistance
TBD
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STL70N4LLF5
Electrical characteristics
Table 7.
Symbol td(on) tr td(off) tf
Switching times
Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions VDD=15 V, ID= 9A, RG=4.7 , VGS=10 V (see Figure 2) Min. Typ. TBD TBD TBD TBD Max. Unit ns ns ns ns
Table 8.
Symbol ISD ISDM(1) VSD(2) trr Qrr IRRM
Source drain diode
Parameter Source-drain current Source-drain current (pulsed) Forward on voltage Reverse recovery time Reverse recovery charge Reverse recovery current ISD = 18A, VGS=0 ISD = 18A, di/dt = 100 A/s, VDD= 25 V TBD TBD TBD Test conditions Min Typ. Max 18 72 1.1 Unit A A V ns nC A
1. Pulse width limited by safe operating area 2. Pulsed: pulse duration=300s, duty cycle 1.5%
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Test circuits
STL70N4LLF5
3
Figure 2.
Test circuits
Switching times test circuit for resistive load Figure 3. Gate charge test circuit
Figure 4.
Test circuit for inductive load Figure 5. switching and diode recovery times
Unclamped inductive load test circuit
Figure 6.
Unclamped inductive waveform
Figure 7.
Switching time waveform
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STL70N4LLF5
Package mechanical data
4
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
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Package mechanical data
STL70N4LLF5
PowerFLATTM(6x5) mechanical data
mm. Min. A A1 A3 b D D1 D2 E E1 E2 E4 e L 0.70 3.43 2.58 4.15 0.35 0.80 Typ. 0.83 0.02 0.20 0.40 5.00 4.75 4.20 6.00 5.75 3.48 2.63 1.27 0.80 0.90 0.027 3.53 2.68 0.135 4.25 0.163 0.47 0.013 Max. 0.93 0.05 Min. 0.031 inch Typ. 0.32 0.0007 0.007 0.015 0.196 0.187 0.165 0.236 0.226 0.137 0.103 0.050 0.031 0.035 0.139 0.105 0.167 0.018 Max. 0.036 0.0019
DIM.
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STL70N4LLF5
Revision history
5
Revision history
Table 9.
Date 01-Dec-2008
Document revision history
Revision 1 First release Changes
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STL70N4LLF5
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